FIGS. 1a to 1d show the process of forming a conventional ULSI MOSFET. As shown in FIG. 1a, P well 10 is formed in a semiconductor substrate. Field oxide layer is formed to define the active region. Impurities are implanted to adjust the threshold voltage and to prevent punch through. Gate oxide 12 is then formed and gate 13 is deposited and defined. Impurities are implanted to form source region and drain region 11.
As shown in FIG. 1b, a silicon dioxide layer is deposited and then etched to form the gate sidewall spacer 14. As shown in FIG. 1c, a metal layer 15 of titanium or nickel is formed on the substrate with a thickness of about 400 to 600 angstrom. Then, a rapid thermal processing (RTP) step is performed so that the gate 13 and the source and drain regions 11 will form metal contacts with the metal layer 15 to prevent the sheet resistivity from being too large due to thin source and drain region 11. After that, a selective etching step is performed. Since the metal layer 15 will not react with the gate sidewall spacer 14, the metal is removed by using an etchant for etching metals. The metal silicide layers 16, i.e. the metal contacts, formed on the gate and the source and drain regions 13, 11 in the rapid thermal process are shown in FIG. 1d. Another rapid thermal process could be performed after the metal layer 15 is removed to further reduce the sheet resistivity.
However, the ULSI MOSFET element produced according to the above procedure has some deficiencies. Since the thickness of the drain and source regions 11 is small, it will be reduced due to the formation of the metal silicide layer 16, and thus, the thickness of the residual drain and source regions will be difficult to control. If the residual drain and source regions are too thin, the leakage current will be too large, and even short circuit may occur. If the residual drain and source regions are too thick, a short channel effect may happen.